PMU Cache-Miss Simulator — v3 · competence basin + four heat maps

L1D PMU counter is the sensor; cache eviction is the actuation. Each walk steps a verified engine (§13a) — it normalizes the miss to n = loss / kE, classifies it against D_basin = 3, scores KL of observed vs the competence basin, checks Coherence Lock at depth N_sat = 5, and ratchets the lane price. This page renders that engine state — it holds no simulation logic.